1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) cell, as well as methods for operating and fabricating a DRAM cell. More specifically, the present invention relates to a one-transistor floating-body DRAM cell formed using a process compatible with a bulk CMOS process, wherein charge is stored inside an electrically isolated body region underneath the transistor channel region.
2. Related Art
Conventional one-transistor, one-capacitor (1T/1C) DRAM cells require a complex process for fabrication. Moreover, significant area is required to form the capacitor needed for storage of signal charge. Recently, one-transistor, floating-body (1T/FB) DRAM cells using partially-depleted silicon-on-insulator (PD-SOI) processes have been proposed, in which a signal charge is stored inside a floating body region, which modulates the threshold voltage (VT) of the transistor. As a result, the separate capacitor of a 1T/FB DRAM cell can be eliminated, thereby resulting in reduced cell area and higher density. Periodic refresh operations are still required for these 1T/FB DRAM cells to counteract the loss of stored charge through junction leakage, gate tunneling leakage and access-induced hot-carrier injections (HCI).
FIG. 1 is a cross-sectional view of a conventional 1T/FB DRAM cell 100 fabricated using a PD-SOI process. DRAM cell 100 includes silicon substrate 101, buried oxide layer 102, oxide regions 103-104, N++ type source and drain regions 105-106, N+ type source and drain regions 107-108, P type floating body region 109, gate oxide 110, gate electrode 111 and sidewall spacers 112-113. Floating body 109 is isolated by gate oxide 110, buried oxide layer 102 and the source and drain depletion regions 107xe2x80x2 and 108xe2x80x2. The partially-depleted floating body 109 is used for storing signal charges that modulate the threshold voltage (VT) of DRAM transistor 100 differently when storing different amount of charge. The source node 105 is typically grounded.
A logic xe2x80x9c1xe2x80x9d data bit is written into DRAM cell 100 by biasing drain node 106 at a high voltage and gate node 111 at a mid-level voltage to induce hot-carrier injection (HCI), whereby hot-holes are injected into floating body node 109, thereby raising the voltage level of floating body node 109, and lowering the threshold voltage (VT) of cell 100. Conversely, a logic xe2x80x9c0xe2x80x9d data bit is written into DRAM cell 100 by biasing drain node 106 to a negative voltage while gate node 111 is biased at a mid-level voltage, thereby forward biasing the floating body-to-drain junction and removing holes from floating body 109, thereby raising the threshold voltage (VT) of cell 100.
A read operation is performed by applying mid-level voltages to both drain node 106 and gate node 111 (while source node 105 remains grounded). Under these conditions, a relatively large drain-to-source current will flow if DRAM cell 100 stores a logic xe2x80x9c1xe2x80x9d data bit, and a relatively small drain-to source current will flow if DRAM cell 100 stores a logic xe2x80x9c0xe2x80x9d data bit. The level of the drain-to-source current is compared with the current through a reference cell to determine the difference between a logic xe2x80x9c0xe2x80x9d and a logic xe2x80x9c1xe2x80x9d data bit. Non-selected DRAM cells in the same array as DRAM cell 100 have their gate nodes biased to a negative voltage to minimize leakage currents and disturbances from read and write operations.
One significant disadvantage of conventional 1T/FB DRAM cell 100 is that it requires the use of partially depleted silicon-on-insulator (PD-SOI) process, which is relatively expensive and not widely available. In addition, the floating body effect of the SOI process, although utilized in the 1T/FB DRAM cell advantageously, complicates circuit and logic designs significantly and often requires costly substrate connections to eliminate undesired floating body nodes not located in the 1T/FB DRAM cells. Further, with a PD-SOI process, the device leakage characteristics can be difficult to control due to the lack of effective back-gate control of the bottom interface of the silicon layer that includes silicon regions 107-109.
Conventional 1T/FB DRAM cells are described in more detail in xe2x80x9cA Capacitor-less 1T-DRAM Cell,xe2x80x9d S. Okhonin et al, pp.85-87, IEEE Electron Device Letters, Vol. 23, No.2, February 2002, and xe2x80x9cMemory Design Using One-Transistor Gain Cell on SOI,xe2x80x9d T. Ohsawa et al, pp.152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002.
Therefore, one object of the present invention is to provide a 1T/FB DRAM cell that is compatible with a conventional bulk CMOS process, and is compatible with conventional logic processes and conventional logic designs.
It is another object of the present invention to provide an electrical isolation junction that can be biased advantageously to minimize sidewall junction leakage and vertical parasitic bipolar leakage currents.
Accordingly, the present invention provides a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell that includes a field-effect transistor fabricated in a semiconductor substrate using a process compatible with a conventional bulk CMOS process. The field-effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type, opposite the first conductivity type, located between the source region and the drain region.
In accordance with the present invention, a buried region of the first conductivity type is located under the source region, drain region and floating body region. The buried region helps to form a depletion region, which is located between the buried region and the source region, the drain region and the floating body region. The floating body region is thereby isolated by the depletion region.
A bias voltage can be applied to the buried region, thereby limiting leakage currents in the 1T/FB DRAM cell. An adjacent well region having the first conductivity type can be used to contact the buried region, thereby enabling the bias voltage to be applied to the buried region via the well region. Alternately, the buried region can be coupled to an underlying deep well region having the first conductivity type, which in turn can be coupled to an adjacent well region of the first conductivity type. In this configuration, a bias voltage can be applied to the buried region via the well region and the deep well region.
If the field-effect transistor is an NMOS transistor (i.e., the first conductivity type is N-type), then the bias voltage can be selected to have a nominal voltage between xe2x88x920.5V to and a VCC supply voltage. Conversely, if the field-effect transistor is a PMOS transistor (i.e., the first conductivity type is p-type), then the bias voltage can be selected to have a nominal voltage between 0 Volts and a VCC supply voltage plus 0.5 Volts. In an alternate embodiment, the buried region can be left in a floating state.
If the field-effect transistor is an NMOS transistor, a logic xe2x80x9c1xe2x80x9d data bit is written to the 1T/FB DRAM cell using a hot carrier injection mechanism, and a logic xe2x80x9c0xe2x80x9d data bit is written to the 1T/FB DRAM cell using a junction forward bias mechanism.
In a particular embodiment, the 1T/FB DRAM cell of the present invention includes one or more shallow trench isolation (STI) regions, each having a bottom surface. The STI regions are located adjacent to the source and drain regions. The buried region is formed such that a top interface of the buried region is located at or above the bottom surfaces of the STI regions (but below the source and drain regions of the cell). The buried region is also formed such that a bottom interface of the buried region is located below the bottom surfaces of the STI regions.
The present invention also includes a method of fabricating a one-transistor, floating-body (1T/FB) dynamic random access memory (DRAM) cell. This method includes forming a buried region having a first conductivity type below the upper surface of a semiconductor region of a semiconductor substrate, the semiconductor region having a second conductivity type, opposite the first conductivity type. After the buried region has been formed, a field-effect transistor is formed in the semiconductor region over the buried region using conventional CMOS processing steps. The buried region results in the formation of a depletion region between the buried region and source, drain and body regions of the field-effect transistor.
In a particular embodiment, the buried region is formed by an ion implantation step, which is performed through a first mask. A threshold voltage adjustment implant for the field-effect transistor can also be performed through the first mask.
The method can also include forming a well region having the first conductivity type in the semiconductor substrate, wherein the buried region contacts the well region. Alternately, the method can include forming a deep well region having the first conductivity type in the semiconductor substrate, wherein the deep well region is located below and continuous with the buried region.
In accordance with another embodiment, a plurality of the 1T/FB DRAM cells of the present invention can be arranged in an array. An area efficient array layout can be implemented, in which adjacent 1T/FB DRAM cells share a common drain region (and a common drain connection), with the depletion region providing adequate isolation between the two 1T-FB DRAM cells.
The present invention will be more fully understood in view of the following description and drawings.